1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. application note 1549 addressing power issues in real time clock applications introduction intersil real time clock (rtc) products now include many products with a variety of functions. common functions include a low power 32,768khz oscillator and also the ability to keep time in sram registers after initial time and date is set. the power for rtc devices includes a v dd source, and can also include a backup source of either a battery or large storage capacitor (super capacitor). in many applications the rtc device is the only device in a system that has an alternative power source such as the backup battery, so there can be unique demands placed on the device compared to other semiconductor products. in addition, the rtc device has a communications bus, usually i 2 c, that has pull-up resistors which can go to a different power source than the rtc. the interrupt or frequency output pull-up can be connected to yet another voltage. some rtc devices contain non-volatile eeprom storage, both for device control registers and for general purpose storage. the eeprom is a robust storage method that can survive temperature extremes, millions of write cycles and up to 10 years of endurance. despite the robust design, there are power and ground voltage transients that, although they exceed data sheet limits, are present in systems and may upset eeprom memory cells. in addition, some applications may have i 2 c communication during power-down, another possible source of upset. rtc device power connections the typical applications circuit for the rtc is shown in figure 1. this seemingly simple circuit has no less than 4 possible power connections: ?v dd power (v power ) ?i 2 c bus open drain pull-up power (v bus ) ? battery backup (v bat ) ? frequency output or interrupt open drain pull-up (v fout ) having four different power sources raises the issue of power sequencing. ideally, the rtc circuit will have 3 of the four power sources in common. the v cc , v bus and v fout should all connect to the main v power source, and when that is the case there are virtually no concerns with power sequencing. many applications prefer to have these connections powered separately. examples include: ? rtc device is powered down while the i 2 c bus and microcontroller are active (not recommended since it will violate rtc data sheet, but rtc devices are ok in this state). ? rtc device is powered down while the f out or irq is pulled up to v bat to allow a wake-up interrupt or clock while other circuits are asleep (this is ok, but the rtc data sheet absolute maximum ratings need to be followed). ? rtc device is powered from a higher or lower voltage than the i 2 c pull-ups (this may or may not be allowed, possible unreliable operation). ? rtc device operates with one supply voltage and the v bat pin is grounded (this is ok, and is covered later in this document). table 1 provides some guidance when designing an rtc applications circuit. v bat v dd scl sda x1 x2 gnd f out 10k v bus c 1 i 2 c bus v power 2.2k 2.2k v fout c 2 bt 1 y 1 figure 1. typical rtc application circuit march 1, 2010 an1549.0
2 an1549.0 march 1, 2010 powering the rtc on and off most intersil rtc devices contain an internal power switch that applies the battery power to the internal circuitry when the v dd voltage drops below a certain threshold. that threshold is generally selectable, depending on the device (see applicable data sheet). since the rtc device is very low power, the switch circuitry is fairly slow, and can take more than 50s to completely switch to the battery voltage. if the v dd power-down ramp is faster than this time, the internal ram registers may not have sufficient voltage to retain their values and may become corrupted or reset altogether. if a v dd power source needs to power-down quickly for some reason, the rtc should have some extra capacitance at the v dd pin to slow down the ramp to >50s. if the extra capacitanc e is not realistic, then a small series resistor can be added to form an r-c network which will give the rtc a dedicated power-down and power-up waveform. since the supply current for rtc?s can go up to 1ma or 2ma during write functions (if eeprom is included), then it?s a good idea to use about a 100 resistor to keep the maximum drop reasonable. power supply turn-on issues some applications involving the rtc device may unknowingly expose the device to excessive transients which may not permanently da mage the device, but may corrupt the eeprom and sram contents. specifically, those applications which use offline ac power and switch it on and off can produce voltage bounces on the ground or v dd , or both, with enough energy and fast enough speed to propagate across a pc board despite bulk and decoupling capacitance at supply pins. in some cases, the energy supplied and the re sulting current pulse is so large and fast that high intensity spikes can occur, capable of producing voltag es exceeding the absolute maximum for ic?s. for negative pulses, the internal esd diodes can absorb this energy but are limited, and the resulting negative excursion can be many volts, triggering latch-up or disrup tive events. the rtc device can be uniquely susceptible to this bounce since it has a battery input and is expected to retain proper data in the sram through power turn-on and turn-off. in cases where the battery input is grounded, a device with eeprom can have the data bits corrupted. it requires a large amount of energy to do this, with device currents and voltages that exceed the absolute maximum ratings. table 1. rtc power connection guidelines description v dd scl sda f out /irq v bat comment 1 normal operation, 5v 5v 5v 5v 5v <5.0v all pull-ups same source as v dd . no issues. ok if v bat is a super capacitor. 2 normal operation, 3.3v 3.3v 3.3v 3.3v 3.3v <3.6v ok. normally v bat up to 5.5v (super capacitor) is ok. check applicable data sheet. 3 split supplies, low voltage four/irq- 5v 5v 5v 3.3v <5.0v ok. the f out can connect to 3.3v circuits reliably. 4 split supplies, lower voltage i 2 c (a) 5v 3.3v 3.3v 5v or 3.3v <5.0v will not work. the v ih for the i 2 c is based on v dd and prevents communications. 5 split supplies, lower voltage i 2 c (b) 5v v bat v bat 5v or 3.3v <3.5v will not work. the v ih for the i 2 c is based on v dd and prevents communications, especially as v bat discharges. v bat discharges quickly too. 6 split supplies, high voltage v bat , variable voltage i 2 c 3.3v v bat v bat 3.3v <5.0v will work on some rtc?s. be careful for v bat > v dd as the device may not access i 2 c in this mode or can draw high v bat current. check applicable data sheet. note that with v bat discharging to 2.0v or below, the v ih will be too low for v dd -referenced i 2 c. v bat discharges quickly too. 7 split supplies, low voltage v bat , variable voltage i 2 c 3.3v v bat v bat 3.3v 3 an1549.0 march 1, 2010 the worst case scenario is where the ac waveform is near its peak during turn-on and the board instantly sees that peak before passive devices absorb the energy. normal power supply filtering does help prevent this, and adding small amounts of inductance can improve it or make it worse, depending on the location of the inductance and decoupling capacitance. the best prevention is to add a medium power schottky diode at the rtc, anode at ground and cathode at v dd , which can clamp the voltage across the device to a safe value at higher currents than the inte rnal esd structures. a good low leakage diode such as the bat54 is recommended. power glitches or interruptions the battery backup design for rtc?s is there to insure the device retains the time/date in the event the power is turned off or interrupted for some reason. battery backup works fine for most applications where the power is turned off and on predictably. occasions arise where there may be fast glitches or excursions of the v dd beyond the absolute maximum limits, and these will cause problems. if a fast glitch is generated by power switching or interruption, then ram contents can be corrupted or reset (see section ?powering the rtc on and off? on page 2). again, local filtering of the v dd may be needed to prevent memory corruption. many intersil rtc devices contain a power-up delay function to prevent accidental access by the serial bus before power is stable and devices on a board are functioning properly. this delay is normally about 90ms, and some older devices may have a 3 second delay. after the glitch or power-up, the delay is triggered and the device will not respond to an i 2 c communication until the timeout period is over. if a customer is unsure about this function in their application, they should contact intersil. powering the rtc with no or very low v bat rtc device operation relies on stable contents in the internal registers. these sram registers get loaded with values either from eeprom or default hard-coded values on power-up, depending on the rtc device type. there are two circuit configurations which lend themselves to corruption of the sram registers: 1. the v bat pin is grounded in this case there is just a main v dd power source which may power-down occasionally. if this voltage is allowed to float to a non-zero stat e on power-down, the ensuing power-up may put the sram registers in an unknown state. practical tests have shown that the sram registers can maintain their contents down to v dd = 1.0v at room temperature. once v dd drops to <0.2v and then rises to its normal level, then the default values will be loaded. with v dd stalled in the range from 0.2v to 1.0v (the ?high risk? range) on power-down, the sram registers can be in an unknown value on power-up. note that the v dd power glitch to this lower voltage for a period of time can also trigger the sram corruption. if the glitch is not recognized by the rest of the system the rtc device can lose sram bits without notice. practical tests show that the glitch would need to be minimum 50s to 100s duration to cause a problem. a solution for corrupted rtc sram on power-up is to add a series resistor and clamp mosfet to the rtc v dd as shown in figure 2. applying a logic high to the rtc_sd node (m 1 gate) will cause m 1 to saturate and discharge c 1 while pulling current through r s . this action clamps the v rtc node (v dd ) low, to around 20mv-30mv or less. when the logic signal is released, c 1 will charge up through r s and v dd will be powered up normally, with registers in the correct default or eeprom recalled states. r s must be chosen so that there enough headroom for the rtc to operate at maximum v dd current, which is normally for an i 2 c write. rtc devices containing eeprom will draw more current, about 1ma during write operations and will need a smaller r s value. v rtc r s v bat * v dd scl sda x1 x2 gnd irq/f out scl sda * also useful if v bat drops to <1.0v r s = 1k for sram devices = 510 for eeprom devices m 1 = fdy301nz or equivalent v sys v sys r 3 r 2 r 1 rtc_sd m 1 c1 figure 2. powering a device with no battery backup application note 1549
4 intersil corporation reserves the right to make changes in circui t design, software and/or specifications at any time without n otice. accordingly, the reader is cautioned to verify that the application note or technical brief is current before proceeding. for information regarding intersil corporation and its products, see www.intersil.com an1549.0 march 1, 2010 a secondary benefit of the r s -c 1 circuit is filtering glitches, preventing unwanted noise on the v dd pin. note that the sda, scl and irq/f out pins all are powered through pull-ups during the v dd power cycle. this state is allowed short term and will not harm the device. 2. v bat is allowed to drop into the high risk range in this case, the backup supply may discharge to a very low voltage (0.2v < v bat < 1v is considered very unreliable for backup power, as well). now the rtc device is relying on v bat bias to power the sram registers and maintain their contents. when the v bat level drops to a low voltage, but not zero, it may be too low to maintain the sram bits and once v dd power is cycled, they will either corrupt the current contents or incorrectly recall the default or eeprom settings. unless the system monitors the battery voltage, it will assume all rtc functions are normal. if the system can detect bad data from the rtc or low v bat has been detected, then the battery should be replaced and the device should restore original sram register settings before operation proceeds. the circuit from figure 3 can be used with the jumper j bat for manually disconnecting the battery to allow the device to reset if the battery or super capacitor is discharged. once the battery is changed or the super capacitor is charged again, the jumper can be replaced. i 2 c communication during power-down most systems will have an orderly power-down sequence, including completing i 2 c communications before complete power voltage shutdown. if that is not possible, then i 2 c communication during battery switchover can occur which may result in erroneous register writes. these register writes could re sult in incorrect data being written to a valid address, or having correct data written to an incorrect address. eith er way, the erroneous write could change data in eeprom (if it exists) or battery backed sram. erroneous data in rtc control registers can result in the device not operating properly, even preventing i 2 c communication with v dd powered up. steps should be taken to prevent any i 2 c activity during v dd power-down situations. conclusions intersil rtc devices are designed to provide a reliable clock and calendar function wi th battery backed up data in registers. there are some power supply situations that need to be considered in order to maintain reliable data and also serial bus communication. with these considerations, rtc applications can be made reliable and robust. figure 3. suggested ba ttery-backup circuit d bat c bat c in bat43w 0.1f 0.1f v dd = 2.7v to 5.5v v bat = 1.8v to 3.2v j bat rtc vdd gnd vbat + application note 1549
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